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Title: Energy Efficiency Limits of Logic and Memory.

Abstract

Abstract not provided.

Authors:
; ; ; ; ; ; ; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-CA), Livermore, CA (United States); Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1373469
Report Number(s):
SAND2016-7245C
646182
DOE Contract Number:
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: Proposed for presentation at the International Conference on Rebooting Computing held October 17-19, 2016 in San Diego, CA.
Country of Publication:
United States
Language:
English

Citation Formats

Agarwal, Sapan, Cook, Jeanine, Debenedictis, Erik, Frank, Michael P, Cauwenburghs, Gert, Srikanth, Sriseshan, Deng, Bobin, Hein, Eric, Rabbat, Paul, and Conte, Thomas. Energy Efficiency Limits of Logic and Memory.. United States: N. p., 2016. Web. doi:10.1109/ICRC.2016.7738676.
Agarwal, Sapan, Cook, Jeanine, Debenedictis, Erik, Frank, Michael P, Cauwenburghs, Gert, Srikanth, Sriseshan, Deng, Bobin, Hein, Eric, Rabbat, Paul, & Conte, Thomas. Energy Efficiency Limits of Logic and Memory.. United States. doi:10.1109/ICRC.2016.7738676.
Agarwal, Sapan, Cook, Jeanine, Debenedictis, Erik, Frank, Michael P, Cauwenburghs, Gert, Srikanth, Sriseshan, Deng, Bobin, Hein, Eric, Rabbat, Paul, and Conte, Thomas. 2016. "Energy Efficiency Limits of Logic and Memory.". United States. doi:10.1109/ICRC.2016.7738676. https://www.osti.gov/servlets/purl/1373469.
@article{osti_1373469,
title = {Energy Efficiency Limits of Logic and Memory.},
author = {Agarwal, Sapan and Cook, Jeanine and Debenedictis, Erik and Frank, Michael P and Cauwenburghs, Gert and Srikanth, Sriseshan and Deng, Bobin and Hein, Eric and Rabbat, Paul and Conte, Thomas},
abstractNote = {Abstract not provided.},
doi = {10.1109/ICRC.2016.7738676},
journal = {},
number = ,
volume = ,
place = {United States},
year = 2016,
month = 7
}

Conference:
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  • Abstract not provided.
  • This paper proposes a new family of counter-type Josephson-junction A/D converters using ultrafast RSFQ logic/memory elements. The converters are built of two main blocks: a low-bit differential-code A/D converter running with sub-terahertz clock speed and a RSFQ-logic-based digital processing unit providing digital low-pass filtering and sample rate reduction. It is shown that such converters can be treated as digital SQUIDs processing extremely high slew rate (up to 10{sup 11} {phi}{sub 0}/s) combined with flux resolution close to that of analog dc SQUIDs (up to 10{sup {minus}6} {phi}{sub 0}Hz{sup {minus}1/2}). Several ways of implementation of both main blocks enabling trade-off ofmore » these parameters against complexity of converter are presented and discussed.« less
  • All refractory Josephson loop logic circuits for a 1Kbit SFQ memory have been developed. The circuit fabircation technology, using NbN/Nb double layered junction formation and reactive ion etching(RIE) with a 2.5 ..mu..m minimum feature size and 1.5 ..mu..m overlay registration, has been utilized. A highly selective and anisotropic RIE process has been performed, in which a CCI/sub 2/F/sub 2/ + Ne gas mixture has been used as etching gases. The experimental circuit consists of address decoders and line drivers, which are based on the principle of current steering in superconducting loops. The decoder and driver were successfully operated with themore » gate current margin of + or - 18% and + or - 14%, respectively. The decoder internal delay time was measured to be about 1.5 ns. It is revealed that these circuits have a satisfactory preformance to be used in the 1Kbit SFQ memory.« less