Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

Journal Article · Tue Jan 03 00:00:00 EST 2017 · Journal of Parallel and Distributed Computing

DOI:https://doi.org/10.1016/j.jpdc.2016.12.009· OSTI ID:1371471

Bender, Michael A. ^[1]; Berry, Jonathan W. ^[2]; Hammond, Simon D. ^[2]; Hemmert, K. Scott ^[2]; McCauley, Samuel ^[1]; Moore, Branden ^[2]; Moseley, Benjamin ^[3]; Phillips, Cynthia A. ^[2]; Resnick, David ^[2]; Rodrigues, Arun ^[2]

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1. Stony Brook Univ., Stony Brook, NY (United States)
2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
3. Washington Univ., St. Louis, MO (United States)

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” and if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.

• Research Organization: Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
• Sponsoring Organization: USDOE National Nuclear Security Administration (NNSA)
• Grant/Contract Number: AC04-94AL85000
• OSTI ID: 1371471
• Alternate ID(s): OSTI ID: 1414597
• Report Number(s): SAND-2015-9641J; PII: S074373151630185X
• Journal Information: Journal of Parallel and Distributed Computing, Vol. 102, Issue C; ISSN 0743-7315
• Publisher: Elsevier
• Country of Publication: United States
• Language: English

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