skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Compensating for Parasitic Voltage Drops in Resistive Memory Arrays.

Abstract

Abstract not provided.

Authors:
; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-CA), Livermore, CA (United States); Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1367275
Report Number(s):
SAND2017-5376C
653440
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: Proposed for presentation at the 2017 IEEE International Memory Workshop held May 14-17, 2017 in Monterey, CA.
Country of Publication:
United States
Language:
English

Citation Formats

Agarwal, Sapan, Schiek, Richard, and Marinella, Matthew. Compensating for Parasitic Voltage Drops in Resistive Memory Arrays.. United States: N. p., 2017. Web. doi:10.1109/IMW.2017.7939075.
Agarwal, Sapan, Schiek, Richard, & Marinella, Matthew. Compensating for Parasitic Voltage Drops in Resistive Memory Arrays.. United States. doi:10.1109/IMW.2017.7939075.
Agarwal, Sapan, Schiek, Richard, and Marinella, Matthew. Mon . "Compensating for Parasitic Voltage Drops in Resistive Memory Arrays.". United States. doi:10.1109/IMW.2017.7939075. https://www.osti.gov/servlets/purl/1367275.
@article{osti_1367275,
title = {Compensating for Parasitic Voltage Drops in Resistive Memory Arrays.},
author = {Agarwal, Sapan and Schiek, Richard and Marinella, Matthew},
abstractNote = {Abstract not provided.},
doi = {10.1109/IMW.2017.7939075},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Mon May 01 00:00:00 EDT 2017},
month = {Mon May 01 00:00:00 EDT 2017}
}

Conference:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that hold this conference proceeding.

Save / Share: