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Title: Fast frequency divider circuit using combinational logic

Abstract

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.

Inventors:
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1360762
Patent Number(s):
9,667,231
Application Number:
15/077,598
Assignee:
Sandia Corporation SNL-A
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2016 Mar 22
Country of Publication:
United States
Language:
English
Subject:
47 OTHER INSTRUMENTATION

Citation Formats

Helinski, Ryan. Fast frequency divider circuit using combinational logic. United States: N. p., 2017. Web.
Helinski, Ryan. Fast frequency divider circuit using combinational logic. United States.
Helinski, Ryan. Tue . "Fast frequency divider circuit using combinational logic". United States. doi:. https://www.osti.gov/servlets/purl/1360762.
@article{osti_1360762,
title = {Fast frequency divider circuit using combinational logic},
author = {Helinski, Ryan},
abstractNote = {The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue May 30 00:00:00 EDT 2017},
month = {Tue May 30 00:00:00 EDT 2017}
}

Patent:

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