skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Fast frequency divider circuit using combinational logic

Patent ·
OSTI ID:1360762

The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation
Patent Number(s):
9,667,231
Application Number:
15/077,598
OSTI ID:
1360762
Resource Relation:
Patent File Date: 2016 Mar 22
Country of Publication:
United States
Language:
English

References (15)

Programmable ring oscillator patent May 1985
Frequency synthesizer using noninteger division and phase selection patent September 1995
Frequency synthesizer patent September 1997
Phase locked loop circuit and method of locking a phase patent September 2008
Method and device for carrying out frequency synthesis in a distance measuring device patent-application October 2003
Phase error cancellation circuit and method for fractional frequency dividers and circuits incorporating same patent-application November 2003
Semiconductor integrated circuit patent-application February 2004
Internal voltage generator for semiconductor memory device patent-application May 2006
System For Generating A Multiple Phase Clock patent-application February 2009
Pulse Receiving Circuit, Pulse Receiving Method And Pulse Wireless Communication Device patent-application February 2009
Jitter Counter And Optical Disc Apparatus Using Same patent-application April 2009
Low power frequency division and local oscillator generation patent-application July 2009
Time-To-Digital Converter and PLL Circuit Using the Same patent-application May 2015
Experimental analysis of a ring oscillator network for hardware trojan detection in a 90nm ASIC conference November 2012
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits journal April 2008

Similar Records

Wideband unbalanced waveguide power dividers and combiners
Patent · Tue May 17 00:00:00 EDT 2016 · OSTI ID:1360762

GATED FREQUENCY DIVIDING CIRCUIT FOR IMPROVED RESOLUTION IN DIGITAL TIME INTERVAL MEASUREMENTS
Technical Report · Fri Jan 01 00:00:00 EST 1960 · OSTI ID:1360762

Josephson modified variable threshold logic gates for use in ultra-high-speed LSI
Journal Article · Wed Feb 01 00:00:00 EST 1989 · IEEE Trans. Electron Devices; (United States) · OSTI ID:1360762

Related Subjects