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Title: Thermally-isolated silicon-based integrated circuits and related methods

Abstract

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Inventors:
; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1356199
Patent Number(s):
9,646,874
Application Number:
13/959,136
Assignee:
Sandia Corporation SNL-A
DOE Contract Number:
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2013 Aug 05
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; 42 ENGINEERING

Citation Formats

Wojciechowski, Kenneth, Olsson, Roy H., Clews, Peggy J., and Bauer, Todd. Thermally-isolated silicon-based integrated circuits and related methods. United States: N. p., 2017. Web.
Wojciechowski, Kenneth, Olsson, Roy H., Clews, Peggy J., & Bauer, Todd. Thermally-isolated silicon-based integrated circuits and related methods. United States.
Wojciechowski, Kenneth, Olsson, Roy H., Clews, Peggy J., and Bauer, Todd. 2017. "Thermally-isolated silicon-based integrated circuits and related methods". United States. doi:. https://www.osti.gov/servlets/purl/1356199.
@article{osti_1356199,
title = {Thermally-isolated silicon-based integrated circuits and related methods},
author = {Wojciechowski, Kenneth and Olsson, Roy H. and Clews, Peggy J. and Bauer, Todd},
abstractNote = {Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = 2017,
month = 5
}

Patent:

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  • Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.
  • A cutoff mesa rib waveguide provides single-mode performance regardless of any deep etches that might be used for electrical isolation between integrated electrooptic devices. Utilizing a principle of a cutoff slab waveguide with an asymmetrical refractive index profile, single mode operation is achievable with a wide range of rib widths and does not require demanding etch depth tolerances. This new waveguide design eliminates reflection effects, or self-interference, commonly seen when conventional rib waveguides are combined with deep isolation etches and thereby reduces high order mode propagation and crosstalk compared to the conventional rib waveguides. 7 figs.
  • A cutoff mesa rib waveguide provides single-mode performance regardless of any deep etches that might be used for electrical isolation between integrated electrooptic devices. Utilizing a principle of a cutoff slab waveguide with an asymmetrical refractive index profile, single mode operation is achievable with a wide range of rib widths and does not require demanding etch depth tolerances. This new waveguide design eliminates reflection effects, or self-interference, commonly seen when conventional rib waveguides are combined with deep isolation etches and thereby reduces high order mode propagation and crosstalk compared to the conventional rib waveguides.
  • This patent describes an improved method for providing silicon dioxide with openings which expose contact pad areas for connections to superconductor in the preparation of superconducting integrated circuits. The method is of the type utilizing depositing of a silicon dioxide film on a substrate which has superconductor on parts of its surface, placing a resist film on the silicon dioxide film, patterning the resist film to expose portions of the silicon dioxide, and reactive ion etching the exposed portions of the silicon dioxide film to expose contact pad areas of superconductor. The improved method comprises: utilizing an etchant gas consistingmore » essentially of 50--95 volume percent nitrogen trifluoride and 5--50 volume percent rare gas for the reactive ion etching of the exposed portions of the silicon dioxide film to expose contact pad areas of superconductor, whereby carbon-containing etchant is not used and polymer by-products of the etching process are essentially completely avoided.« less
  • This patent describes a computer-aided design system for designing an application specific integrated circuit directly from architecture independent functional specifications for the integrated circuit. It comprises: a macro library defining a set of architecture independent operations comprised of actions and conditions; input specification means operable by a user for defining architecture independent functional specifications for the integrated circuit; a cell library; cell selector means; and net list generator means.