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Title: Fast process flow, on-wafer interconnection and singulation for MEPV

Abstract

A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

Inventors:
; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1341870
Patent Number(s):
9,559,219
Application Number:
14/745,251
Assignee:
Sandia Corporation (Albuquerque, NM) SNL-A
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Patent
Resource Relation:
Patent File Date: 2015 Jun 19
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

Okandan, Murat, Nielson, Gregory N., Cruz-Campa, Jose Luis, and Sanchez, Carlos Anthony. Fast process flow, on-wafer interconnection and singulation for MEPV. United States: N. p., 2017. Web.
Okandan, Murat, Nielson, Gregory N., Cruz-Campa, Jose Luis, & Sanchez, Carlos Anthony. Fast process flow, on-wafer interconnection and singulation for MEPV. United States.
Okandan, Murat, Nielson, Gregory N., Cruz-Campa, Jose Luis, and Sanchez, Carlos Anthony. Tue . "Fast process flow, on-wafer interconnection and singulation for MEPV". United States. doi:. https://www.osti.gov/servlets/purl/1341870.
@article{osti_1341870,
title = {Fast process flow, on-wafer interconnection and singulation for MEPV},
author = {Okandan, Murat and Nielson, Gregory N. and Cruz-Campa, Jose Luis and Sanchez, Carlos Anthony},
abstractNote = {A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Jan 31 00:00:00 EST 2017},
month = {Tue Jan 31 00:00:00 EST 2017}
}

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