Schedulers with load-store queue awareness
Patent
·
OSTI ID:1340538
In one embodiment, a computer-implemented method includes tracking a size of a load-store queue (LSQ) during compile time of a program. The size of the LSQ is time-varying and indicates how many memory access instructions of the program are on the LSQ. The method further includes scheduling, by a computer processor, a plurality of memory access instructions of the program based on the size of the LSQ.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B599858
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
- Patent Number(s):
- 9,552,196
- Application Number:
- 14/744,051
- OSTI ID:
- 1340538
- Resource Relation:
- Patent File Date: 2015 Jun 19
- Country of Publication:
- United States
- Language:
- English
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
|
patent | September 1996 |
Scheduling instructions with different latencies
|
patent | March 2000 |
Method for alternate preferred time delivery of load data
|
patent | May 2002 |
System and method for scheduling instructions to maximize outstanding prefetches and loads
|
patent | July 2005 |
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