skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Multiprocessor system with multiple concurrent modes of execution

Patent ·
OSTI ID:1333218
; ; ; ; ;

A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
9,501,333
Application Number:
14/143,783
OSTI ID:
1333218
Resource Relation:
Patent File Date: 2013 Dec 30
Country of Publication:
United States
Language:
English

References (79)

Odd boundary address aligned direct memory acess device and method patent December 1992
Processor associated blocking symbol controls for serializing the accessing of data resources in a computer system patent April 1999
Eviction override for larx-reserved addresses patent April 2001
Apparatus and method for preventing cache data eviction during an atomic operation patent February 2002
System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture patent March 2002
Detecting full conditions in a queue patent October 2002
Information processing apparatus with cache coherency patent May 2003
Architectural support for thread level speculative execution patent March 2008
Speculative multiaddress atomicity patent May 2008
Low complexity speculative multithreading system based on unmodified microprocessor core patent July 2008
Synchronization of parallel processes using speculative execution of synchronization instructions patent March 2009
Method and apparatus for enforcing memory reference ordering requirements at the L1 cache level patent April 2009
Safe store for speculative helper threads patent February 2010
Verification of memory consistency and transactional memory patent October 2010
Low complexity speculative multithreading system based on unmodified microprocessor core patent November 2010
Automated partitioning of a computation for parallel or other high capability architecture patent November 2011
Transactional memory in out-of-order processors patent May 2012
Enabling speculative state information in a cache coherency protocol patent May 2012
Context switching and synchronization patent June 2012
Parallelizing single threaded programs by performing look ahead operation on the single threaded program to identify plurality of instruction threads prior to execution patent July 2013
Transactional block conflict resolution based on the determination of executing threads in parallel or in serial mode patent September 2013
Method and apparatus for scheduling multiple threads for execution in a shared microprocessor pipeline patent June 2014
System and method for reducing serialization in transactional memory using gang release of blocked threads patent July 2014
Multi-thread packet processor patent-application June 2002
Cache way prediction based on instruction base register patent-application September 2002
Using an L2 directory to facilitate speculative loads in a multiprocessor system patent-application December 2002
Fast and accurate cache way selection patent-application January 2003
Stall technique to facilitate atomicity in processor execution of helper set patent-application September 2004
Synchronization of parallel processes patent-application September 2005
System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory patent-application February 2006
Memory controller and method for optimized read/modify/write performance patent-application April 2006
Processor with cache way prediction and method thereof patent-application May 2006
Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache patent-application June 2006
Transaction based shared data operations in a multiprocessor environment patent-application July 2006
Implementation of load linked and store conditional operations patent-application July 2006
Apparatus and method for sparse line write transactions patent-application February 2007
Thread-Shared Software Code Caches patent-application March 2007
Separate data/coherency caches in a shared memory multiprocessor system patent-application July 2007
Architectural support for thread level speculative execution patent-application August 2007
Snoop Filter Directory Mechanism in Coherency Shared Memory System patent-application December 2007
Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches patent-application August 2008
Low Complexity Speculative Multithreading System Based on Unmodified Microprocessor Core patent-application October 2008
Computing System with Transactional Memory Using Millicode Assists patent-application November 2008
Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory patent-application December 2008
Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups patent-application December 2008
Speculative Memory Prefetch patent-application January 2009
System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions patent-application January 2009
Enabling Speculative State Information in a Cache Coherency Protocol patent-application March 2009
Strand-Based Computing Hardware and Dynamically Optimizing Strandware for a High Performance Microprocessor System patent-application June 2009
System and Method for Handling Overflow in Hardware Transactional Memory with Locks patent-application July 2009
Efficient Deterministic Multiprocessing patent-application September 2009
Early header CRC in data response packets with variable gap count patent-application October 2009
Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System patent-application November 2009
Methods and apparatuses for improving speculation success in processors patent-application May 2010
Cache control device and control method patent-application July 2010
Using Time Stamps to Facilitate Load Reordering patent-application August 2010
Multi-Domain Management of a Cache in a Processor System patent-application September 2010
Using Domains for Physical Address Management in a Multiprocessor System patent-application September 2010
Hierarchical Bloom Filters for Facilitating Concurrency Control patent-application December 2010
Transactional Conflict Resolution Based on Locality patent-application January 2011
Detecting Task Complete Dependencies Using Underlying Speculative Multi-Threading Hardware patent-application March 2011
Store Aware Prefetching for a Datastream patent-application March 2011
Conditional Load Store in a Shared Cache patent-application May 2011
Atomic Commit Predicated on Consistency of Watches patent-application June 2011
Cache Spill Management Techniques patent-application June 2011
Physical Aliasing for Thread Level Speculation with a Speculation Blind Cache patent-application August 2011
Pre-Fetching for a Sibling Cache patent-application September 2011
Speculative synchronization: applying thread-level speculation to explicitly parallel applications
  • Martínez, José F.; Torrellas, Josep
  • Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) - ASPLOS '02 https://doi.org/10.1145/605397.605400
conference January 2002
A quantitative assessment of thread-level speculation techniques conference January 2000
Bulk Disambiguation of Speculative Threads in Multiprocessors conference January 2006
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation conference January 2005
Active memory operations conference January 2007
Fast synchronization on shared-memory multiprocessors: An architectural approach journal October 2005
Scatter-Add in Data Parallel Architectures conference January 2005
Algorithms for scalable synchronization on shared-memory multiprocessors journal February 1991
Nonblocking Algorithms and Preemption-Safe Locking on Multiprogrammed Shared Memory Multiprocessors journal May 1998
A fetch-and-op implementation for parallel computers journal May 1988
Wait-free synchronization journal January 1991
Designing a Common Communication Subsystem book January 2005

Similar Records

Related Subjects

97 MATHEMATICS AND COMPUTING