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Title: Multiple core computer processor with globally-accessible local memories

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

Inventors:
; ;
Publication Date:
Research Org.:
Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1325760
Patent Number(s):
9,448,940
Application Number:
14/354,257
Assignee:
The Regents of the University of California (Oakland, CA) LBNL
DOE Contract Number:
AC02-05CH11231
Resource Type:
Patent
Resource Relation:
Patent File Date: 2012 Oct 26
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Shalf, John, Donofrio, David, and Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States: N. p., 2016. Web.
Shalf, John, Donofrio, David, & Oliker, Leonid. Multiple core computer processor with globally-accessible local memories. United States.
Shalf, John, Donofrio, David, and Oliker, Leonid. 2016. "Multiple core computer processor with globally-accessible local memories". United States. doi:. https://www.osti.gov/servlets/purl/1325760.
@article{osti_1325760,
title = {Multiple core computer processor with globally-accessible local memories},
author = {Shalf, John and Donofrio, David and Oliker, Leonid},
abstractNote = {A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = 2016,
month = 9
}

Patent:

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