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Title: Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts

Abstract

Mention the words ''stress voiding'', and everyone from technology engineer to manager to customer is likely to cringe. This IC failure mechanism elicits fear because it is insidious, capricious, and difficult to identify and arrest. There are reasons to believe that a damascene-copper future might be void-free. Nevertheless, engineers who continue to produce ICs with Al-alloy interconnects, or who assess the reliability of legacy ICs with long service life, need up-to-date insights and techniques to deal with stress voiding problems. Stress voiding need not be fearful. Not always predictable, neither is it inevitable. On the contrary, stress voids are caused by specific, avoidable processing errors. Analytical work, though often painful, can identify these errors when stress voiding occurs, and vigilance in monitoring the improved process can keep it from recurring. In this article, they show that a methodical, forensics approach to failure analysis can solve suspected cases of stress voiding. This approach uses new techniques, and patiently applies familiar ones, to develop evidence meeting strict standards of proof.

Authors:
Publication Date:
Research Org.:
Sandia National Labs., Albuquerque, NM (US); Sandia National Labs., Livermore, CA (US)
Sponsoring Org.:
US Department of Energy (US)
OSTI Identifier:
12671
Report Number(s):
SAND99-2361J
TRN: AH200120%%462
DOE Contract Number:  
AC04-94AL85000
Resource Type:
Journal Article
Journal Name:
Electronic Device Failure Analysis News
Additional Journal Information:
Other Information: Submitted to Electronic Device Failure Analysis News; PBD: 17 Sep 1999
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; ENGINEERS; MONITORING; RELIABILITY; SERVICE LIFE; ALUMINIUM ALLOYS

Citation Formats

FILTER, WILLIAM F. Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts. United States: N. p., 1999. Web.
FILTER, WILLIAM F. Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts. United States.
FILTER, WILLIAM F. Fri . "Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts". United States. https://www.osti.gov/servlets/purl/12671.
@article{osti_12671,
title = {Stress Voiding in IC Interconnects - Rules of Evidence for Failure Analysts},
author = {FILTER, WILLIAM F.},
abstractNote = {Mention the words ''stress voiding'', and everyone from technology engineer to manager to customer is likely to cringe. This IC failure mechanism elicits fear because it is insidious, capricious, and difficult to identify and arrest. There are reasons to believe that a damascene-copper future might be void-free. Nevertheless, engineers who continue to produce ICs with Al-alloy interconnects, or who assess the reliability of legacy ICs with long service life, need up-to-date insights and techniques to deal with stress voiding problems. Stress voiding need not be fearful. Not always predictable, neither is it inevitable. On the contrary, stress voids are caused by specific, avoidable processing errors. Analytical work, though often painful, can identify these errors when stress voiding occurs, and vigilance in monitoring the improved process can keep it from recurring. In this article, they show that a methodical, forensics approach to failure analysis can solve suspected cases of stress voiding. This approach uses new techniques, and patiently applies familiar ones, to develop evidence meeting strict standards of proof.},
doi = {},
journal = {Electronic Device Failure Analysis News},
number = ,
volume = ,
place = {United States},
year = {1999},
month = {9}
}