Activation Energies for Oxide- and Interface-Trap Charge Generation Due to Negative-Bias Temperature Stress of Si-Capped SiGe-pMOSFETs
- Vanderbilt Univ., Nashville, TN (United States)
- Pennsylvania State Univ., Erie, PA (United States)
- IMEC, Leuven (Belgium)
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Here, we investigate negative-bias temperature instabilities in SiGe pMOSFETs with SiO2/HfO2 gate dielectrics. The activation energies we measured for interface-trap charge buildup during negative-bias temperature stress were lower for SiGe channel pMOSFETs with SiO2/HfO2 gate dielectrics and Si capping layers than for conventional Si channel pMOSFETs with SiO2 gate dielectrics. Electron energy loss spectroscopy and scanning transmission electron microscopy images demonstrate that Ge atoms can diffuse from the SiGe layer into the Si capping layer, which is adjacent to the SiO2/HfO2 gate dielectric. Density functional calculations show that these Ge atoms reduce the strength of nearby Si-H bonds and that Ge-H bond energies are still lower, thereby reducing the activation energy for interface-trap generation for the SiGe devices. Moreover, activation energies for oxide-trap charge buildup during negative-bias temperature stress are similarly small for SiGe pMOSFETs with SiO2/HfO2 gate dielectrics and Si pMOSFETs with SiO2 gate dielectrics, suggesting that, in both cases, the oxide-trap charge buildup likely is rate-limited by hole tunneling into the near-interfacial SiO2.
- Research Organization:
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC), Basic Energy Sciences (BES)
- DOE Contract Number:
- AC05-00OR22725
- OSTI ID:
- 1265830
- Journal Information:
- IEEE Transactions on Device and Materials Reliability, Vol. 15, Issue 3; ISSN 1530-4388
- Publisher:
- IEEE
- Country of Publication:
- United States
- Language:
- English
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