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Title: EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches

Abstract

Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased and hence, the researchers have explored non-volatile memories (NVMs) which provide high density and consume low-leakage power. Since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving reasonable cache lifetimes using NVMs. We present EqualWrites, a technique for mitigating intra-set write variation. In this paper, our technique works by recording the number of writes on a block and changing the cache-block location of a hot data-item to redirect the future writes to a cold block to achieve wear-leveling. Simulation experiments have been performed using an x86-64 simulator and benchmarks from SPEC06 and HPC (high-performance computing) field. The results show that for single, dual and quad-core system configurations, EqualWrites improves cache lifetime by 6.31X, 8.74X and 10.54X, respectively. In addition, its implementation overhead is very small and it provides larger improvement in lifetime than three other intra-set wear-leveling techniques and a cache replacement policy.

Authors:
 [1];  [1]
  1. Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Publication Date:
Research Org.:
Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
Sponsoring Org.:
USDOE Office of Science (SC)
OSTI Identifier:
1265263
Grant/Contract Number:  
AC05-00OR22725
Resource Type:
Journal Article: Accepted Manuscript
Journal Name:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Additional Journal Information:
Journal Name: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Journal Volume: 24; Journal Issue: 1; Journal ID: ISSN 1063-8210
Publisher:
IEEE
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; Cache memory; device lifetime; intra-set write variation (WV); non-volatile memory (NVM or NVRAM); wear leveling

Citation Formats

Mittal, Sparsh, and Vetter, Jeffrey S. EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches. United States: N. p., 2015. Web. doi:10.1109/TVLSI.2015.2389113.
Mittal, Sparsh, & Vetter, Jeffrey S. EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches. United States. doi:10.1109/TVLSI.2015.2389113.
Mittal, Sparsh, and Vetter, Jeffrey S. Thu . "EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches". United States. doi:10.1109/TVLSI.2015.2389113. https://www.osti.gov/servlets/purl/1265263.
@article{osti_1265263,
title = {EqualWrites: Reducing Intra-set Write Variations for Enhancing Lifetime of Non-volatile Caches},
author = {Mittal, Sparsh and Vetter, Jeffrey S.},
abstractNote = {Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased and hence, the researchers have explored non-volatile memories (NVMs) which provide high density and consume low-leakage power. Since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving reasonable cache lifetimes using NVMs. We present EqualWrites, a technique for mitigating intra-set write variation. In this paper, our technique works by recording the number of writes on a block and changing the cache-block location of a hot data-item to redirect the future writes to a cold block to achieve wear-leveling. Simulation experiments have been performed using an x86-64 simulator and benchmarks from SPEC06 and HPC (high-performance computing) field. The results show that for single, dual and quad-core system configurations, EqualWrites improves cache lifetime by 6.31X, 8.74X and 10.54X, respectively. In addition, its implementation overhead is very small and it provides larger improvement in lifetime than three other intra-set wear-leveling techniques and a cache replacement policy.},
doi = {10.1109/TVLSI.2015.2389113},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
number = 1,
volume = 24,
place = {United States},
year = {Thu Jan 29 00:00:00 EST 2015},
month = {Thu Jan 29 00:00:00 EST 2015}
}

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