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Title: Integrated circuit test-port architecture and method and apparatus of test-port generation

Patent ·
OSTI ID:1246915

A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC04-94AL85000
Assignee:
Sandia Corporation (Albuquerque, NM)
Patent Number(s):
9,311,444
Application Number:
14/328,379
OSTI ID:
1246915
Resource Relation:
Patent File Date: 2014 Jul 10
Country of Publication:
United States
Language:
English

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