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Title: Linear array implementation of the EM algorithm for PET image reconstruction

Abstract

The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution back projection algorithms. However, the PET image reconstruction based on the EM algorithm is computationally burdensome for today`s single processor systems. In addition, a large memory is required for the storage of the image, projection data, and the probability matrix. Since the computations are easily divided into tasks executable in parallel, multiprocessor configurations are the ideal choice for fast execution of the EM algorithms. In tis study, the authors attempt to overcome these two problems by parallelizing the EM algorithm on a multiprocessor systems. The parallel EM algorithm on a linear array topology using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PE`s) has been implemented. The performance of the EM algorithm on a 386/387 machine, IBM 6000 RISC workstation, and on the linear array system is discussed and compared. The results show that the computational speed performance of a linear array using 8 DSP chips as PE`s executing the EM image reconstruction algorithm is about 15.5 times better than that of the IBM 6000 RISC workstation. The novelty of the scheme is its simplicity. Themore » linear array topology is expandable with a larger number of PE`s. The architecture is not dependant on the DSP chip chosen, and the substitution of the latest DSP chip is straightforward and could yield better speed performance.« less

Authors:
; ;  [1]
  1. Indian Institute of Science, Bangalore (India)
Publication Date:
OSTI Identifier:
119014
Resource Type:
Journal Article
Resource Relation:
Journal Name: IEEE Transactions on Nuclear Science; Journal Volume: 42; Journal Issue: 4; Other Information: PBD: Aug 1995
Country of Publication:
United States
Language:
English
Subject:
55 BIOLOGY AND MEDICINE, BASIC STUDIES; 99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; POSITRON COMPUTED TOMOGRAPHY; IMAGE PROCESSING; ALGORITHMS; ARRAY PROCESSORS; PARALLEL PROCESSING; IBM COMPUTERS; PERFORMANCE; COMPARATIVE EVALUATIONS; COMPUTER ARCHITECTURE

Citation Formats

Rajan, K., Patnaik, L.M., and Ramakrishna, J. Linear array implementation of the EM algorithm for PET image reconstruction. United States: N. p., 1995. Web. doi:10.1109/23.467723.
Rajan, K., Patnaik, L.M., & Ramakrishna, J. Linear array implementation of the EM algorithm for PET image reconstruction. United States. doi:10.1109/23.467723.
Rajan, K., Patnaik, L.M., and Ramakrishna, J. 1995. "Linear array implementation of the EM algorithm for PET image reconstruction". United States. doi:10.1109/23.467723.
@article{osti_119014,
title = {Linear array implementation of the EM algorithm for PET image reconstruction},
author = {Rajan, K. and Patnaik, L.M. and Ramakrishna, J.},
abstractNote = {The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution back projection algorithms. However, the PET image reconstruction based on the EM algorithm is computationally burdensome for today`s single processor systems. In addition, a large memory is required for the storage of the image, projection data, and the probability matrix. Since the computations are easily divided into tasks executable in parallel, multiprocessor configurations are the ideal choice for fast execution of the EM algorithms. In tis study, the authors attempt to overcome these two problems by parallelizing the EM algorithm on a multiprocessor systems. The parallel EM algorithm on a linear array topology using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PE`s) has been implemented. The performance of the EM algorithm on a 386/387 machine, IBM 6000 RISC workstation, and on the linear array system is discussed and compared. The results show that the computational speed performance of a linear array using 8 DSP chips as PE`s executing the EM image reconstruction algorithm is about 15.5 times better than that of the IBM 6000 RISC workstation. The novelty of the scheme is its simplicity. The linear array topology is expandable with a larger number of PE`s. The architecture is not dependant on the DSP chip chosen, and the substitution of the latest DSP chip is straightforward and could yield better speed performance.},
doi = {10.1109/23.467723},
journal = {IEEE Transactions on Nuclear Science},
number = 4,
volume = 42,
place = {United States},
year = 1995,
month = 8
}
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