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Title: An evaluation of MPI message rate on hybrid-core processors

Journal Article · · International Journal of High Performance Computing Applications
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  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Scalable System Software
  2. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States). Scalable Computer Architecture

Power and energy concerns are motivating chip manufacturers to consider future hybrid-core processor designs that may combine a small number of traditional cores optimized for single-thread performance with a large number of simpler cores optimized for throughput performance. This trend is likely to impact the way in which compute resources for network protocol processing functions are allocated and managed. In particular, the performance of MPI match processing is critical to achieving high message throughput. In this paper, we analyze the ability of simple and more complex cores to perform MPI matching operations for various scenarios in order to gain insight into how MPI implementations for future hybrid-core processors should be designed.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA)
Grant/Contract Number:
AC04-94AL85000
OSTI ID:
1185011
Report Number(s):
SAND-2014-20472J; 547795
Journal Information:
International Journal of High Performance Computing Applications, Vol. 28, Issue 4; ISSN 1094-3420
Country of Publication:
United States
Language:
English
Citation Metrics:
Cited by: 17 works
Citation information provided by
Web of Science

References (5)

The impact of hybrid-core processors on MPI message rate conference January 2013
An application based MPI message throughput benchmark conference August 2009
Implementation and evaluation of shared-memory communication and synchronization operations in MPICH2 using the Nemesis communication subsystem journal September 2007
A high-performance, portable implementation of the MPI message passing interface standard journal September 1996
The impact of MPI queue usage on message latency conference January 2004

Cited By (4)

Communication‐aware message matching in MPI
  • Ghazimirsaeed, S. Mahdieh; Mirsadeghi, Seyed H.; Afsahi, Ahmad
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3 https://doi.org/10.1002/cpe.4862
journal September 2018
Hardware MPI message matching: Insights into MPI matching behavior to inform design
  • Ferreira, Kurt; Grant, Ryan E.; Levenhagen, Michael J.
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3 https://doi.org/10.1002/cpe.5150
journal February 2019
Tail queues: A multi‐threaded matching architecture
  • Dosanjh, Matthew G. F.; Grant, Ryan E.; Schonbein, Whit
  • Concurrency and Computation: Practice and Experience, Vol. 32, Issue 3 https://doi.org/10.1002/cpe.5158
journal February 2019
The survey on ARM processors for HPC journal June 2019