skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Composite patterning devices for soft lithography

Abstract

The present invention provides methods, devices and device components for fabricating patterns on substrate surfaces, particularly patterns comprising structures having microsized and/or nanosized features of selected lengths in one, two or three dimensions. The present invention provides composite patterning devices comprising a plurality of polymer layers each having selected mechanical properties, such as Young's Modulus and flexural rigidity, selected physical dimensions, such as thickness, surface area and relief pattern dimensions, and selected thermal properties, such as coefficients of thermal expansion, to provide high resolution patterning on a variety of substrate surfaces and surface morphologies.

Inventors:
;
Publication Date:
Research Org.:
The Board of Trustees of the University of Illinois, Urbana, IL (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1176164
Patent Number(s):
7,195,733
Application Number:
11/115,954
Assignee:
The Board of Trustees of the University of Illinois (Urbana, IL) OSTI
DOE Contract Number:
FG02-91ER45439
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE

Citation Formats

Rogers, John A., and Menard, Etienne. Composite patterning devices for soft lithography. United States: N. p., 2007. Web.
Rogers, John A., & Menard, Etienne. Composite patterning devices for soft lithography. United States.
Rogers, John A., and Menard, Etienne. Tue . "Composite patterning devices for soft lithography". United States. doi:. https://www.osti.gov/servlets/purl/1176164.
@article{osti_1176164,
title = {Composite patterning devices for soft lithography},
author = {Rogers, John A. and Menard, Etienne},
abstractNote = {The present invention provides methods, devices and device components for fabricating patterns on substrate surfaces, particularly patterns comprising structures having microsized and/or nanosized features of selected lengths in one, two or three dimensions. The present invention provides composite patterning devices comprising a plurality of polymer layers each having selected mechanical properties, such as Young's Modulus and flexural rigidity, selected physical dimensions, such as thickness, surface area and relief pattern dimensions, and selected thermal properties, such as coefficients of thermal expansion, to provide high resolution patterning on a variety of substrate surfaces and surface morphologies.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Mar 27 00:00:00 EDT 2007},
month = {Tue Mar 27 00:00:00 EDT 2007}
}

Patent:

Save / Share:
  • A photolithographic process forms patterns on HgI.sub.2 surfaces and defines metal sublimation masks and electrodes to substantially improve device performance by increasing the realizable design space. Techniques for smoothing HgI.sub.2 surfaces and for producing trenches in HgI.sub.2 are provided. A sublimation process is described which produces etched-trench devices with enhanced electron-transport-only behavior.
  • Simplified methods of multiple-patterning photolithography using sequential infiltration synthesis to modify the photoresist such that it withstands plasma etching better than unmodified resist and replaces one or more hard masks and/or a freezing step in MPL processes including litho-etch-litho-etch photolithography or litho-freeze-litho-etch photolithography.
  • A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.
  • Three-dimensional patterning methods of a three-dimensional microstructure, such as a semiconductor wire array, are described, in conjunction with etching and/or deposition steps to pattern the three-dimensional microstructure.
  • A method is described for patterning subsurface dislocation features in a semiconductor device, wherein said semiconductor device includes a semiconductor substrate and a strained semiconductor layer, the method comprising: (a) creating a pattern of semiconductor material on said semiconductor device, said deposited material is of a thickness which thermodynamically stabilizes areas of said strained semiconductor layer that lie beneath said pattern; and (b) generating a plurality of dislocations in select areas of said strained semiconductor layer by applying heat to said semiconductor device to cause a relaxation in areas of said strained layer which do not lie beneath said semiconductormore » material pattern, thereby creating said plurality of dislocations in said relaxed areas.« less