Size reduction techniques for vital compliant VHDL simulation models
Patent
·
OSTI ID:1175858
A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States); Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 7,085,701
- Application Number:
- 10/038,311
- OSTI ID:
- 1175858
- Resource Relation:
- Patent File Date: 2002 Jan 02
- Country of Publication:
- United States
- Language:
- English
Modeling ASIC memories in VHDL
|
conference | January 1996 |
OLIVIA: object oriented logic simulation implementing the VITAL standard
|
conference | January 1997 |
Standardizing ASIC libraries in VHDL using VITAL: a tutorial
|
conference | January 1995 |
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