Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

Title: Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

Full Record
Other Related Research

Abstract

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Inventors:: Manginell, Ronald P.; Schubert, W. Kent; Shul, Randy J.

Publication Date:: 2005-08-16

Research Org.:: Sandia National Lab. (SNL-CA), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1175465

Patent Number(s):: 6,930,051

Application Number:: 10/165,861

Assignee:: Sandia Corporation

DOE Contract Number:: AC04-94AL85000

Resource Type:: Patent

Country of Publication:: United States

Language:: English

Subject:: 77 NANOSCIENCE AND NANOTECHNOLOGY

Citation Formats


                    Manginell, Ronald P., Schubert, W. Kent, and Shul, Randy J. Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer.  United States: N. p., 2005. 
        Web.

Copy to clipboard


                    Manginell, Ronald P., Schubert, W. Kent, & Shul, Randy J. Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer.  United States.

Copy to clipboard


                    Manginell, Ronald P., Schubert, W. Kent, and Shul, Randy J. Tue .  
        "Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer".  United States.  https://www.osti.gov/servlets/purl/1175465.

Copy to clipboard


                    
@article{osti_1175465,

  title        = {Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer},

  author       = {Manginell, Ronald P. and Schubert, W. Kent and Shul, Randy J.},

  abstractNote = {New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.},

  doi          = {},

  url          = {https://www.osti.gov/biblio/1175465},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2005},

  month        = {8}

}

Copy to clipboard

Patent:

View Patent

Save / Share:

Export Metadata

Save to My Library

Similar records in OSTI.GOV collections:

Method to control artifacts of microstructural fabrication

Patent Shul, Randy J. ; Willison, Christi G. ; Schubert, W. Kent ; ...

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.
Full Text Available
Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch

Patent Morales, Alfredo M. ; Gonzales, Marcela

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch themore »« less
Full Text Available
Fabrication of Very-High-Aspect-Ratio Microstructures in Complex Patterns by Photoelectrochemical Etching

Journal Article Sun, GY ; Zhao, X ; Kim, CJ - Journal of Microelectromechanical Systems

We have fabricated very-high-aspect-ratio (VHAR) silicon and metal microstructures in complex geometric patterns. The recently developed surfactant-added tetramethylammonium hydroxide etching allows the formation of V-grooves in any pattern, i.e., not limited by the crystal direction, on a silicon surface. As the resulting sharp pits allow very deep photoelectrochemical etching, VHAR silicon microstructures (4-mu m-wide and over-300-mu m-deep trenches) are successfully fabricated in complex patterns (spiral and zigzag demonstrated), overcoming the prevailing limitations of simple pores and straight trenches. Furthermore, by filling the VHAR silicon mold with nickel and removing the silicon, high-aspect-ratio metal microstructures of complex patterns are also obtained.more »« less
https://doi.org/10.1109/JMEMS.2012.2211574
Precision fabrication of large area silicon-based geometrically enhanced x-ray photocathodes using plasma etching

Conference Koch, Jeffrey A. ; Grim, Gary P. ; Opachich, Y. P. ; ... - Proceedings of SPIE - The International Society for Optical Engineering

Geometrically enhanced photocathodes are currently being developed for use in applications that seek to improve detector efficiency in the visible to X-ray ranges. Various photocathode surface geometries are typically chosen based on the detector operational wavelength region, along with requirements such as spatial resolution, temporal resolution and dynamic range. Recently, a structure has been identified for possible use in the X-ray region. This anisotropic high aspect ratio structure has been produced in silicon using inductively coupled plasma (ICP) etching technology. The process is specifically developed with respect to the pattern density and geometry of the photocathode chip to achieve themore »« less
https://doi.org/10.1117/12.2186622

Full Text Available
Damaged silicon contact layer removal using atomic layer etching for deep-nanoscale semiconductor devices

Journal Article Kim, Jong Kyu ; Cho, Sung Il ; Lee, Sung Ho ; ... - Journal of Vacuum Science and Technology. A, Vacuum, Surfaces and Films

Silicon atomic layer etching (ALET) using Cl{sub 2} is applied to remove the damaged layer on a 30 nm contact silicon surface formed by high-energy reactive ions during high aspect ratio contact etching, and its effects on the damage removal characteristics are investigated. Compared to a conventional damage removal method, such as the low-power CF{sub 4} plasma treatment technique, ALET produces less secondary damage to the substrate and gives exact etch depth control and extremely high etch selectivity to the contact SiO{sub 2} insulating pattern mold. When ALET is applied after a conventional damage removal technique, the sheet resistance ofmore »« less
https://doi.org/10.1116/1.4823335

Similar Records