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Title: Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates

Abstract

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

Inventors:
; ; ;
Publication Date:
Research Org.:
The Board of Trustees of the University of Illinois, Urbana, IL (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1169084
Patent Number(s):
8,946,683
Application Number:
12/996,924
Assignee:
The Board of Trustees of the University of Illinois (Urbana, IL) CHO
DOE Contract Number:
FG02-07ER46471
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY

Citation Formats

Rogers, John A, Cao, Qing, Alam, Muhammad, and Pimparkar, Ninad. Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates. United States: N. p., 2015. Web.
Rogers, John A, Cao, Qing, Alam, Muhammad, & Pimparkar, Ninad. Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates. United States.
Rogers, John A, Cao, Qing, Alam, Muhammad, and Pimparkar, Ninad. Tue . "Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates". United States. doi:. https://www.osti.gov/servlets/purl/1169084.
@article{osti_1169084,
title = {Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates},
author = {Rogers, John A and Cao, Qing and Alam, Muhammad and Pimparkar, Ninad},
abstractNote = {The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 03 00:00:00 EST 2015},
month = {Tue Feb 03 00:00:00 EST 2015}
}

Patent:

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  • This disclosure provides systems, methods, and apparatus for flexible thin-film transistors. In one aspect, a device includes a polymer substrate, a gate electrode disposed on the polymer substrate, a dielectric layer disposed on the gate electrode and on exposed portions of the polymer substrate, a carbon nanotube network disposed on the dielectric layer, and a source electrode and a drain electrode disposed on the carbon nanotube network.
  • Single-walled carbon nanotubes (SWCNTs) are promising materials as active channels for flexible transistors owing to their excellent electrical and mechanical properties. However, flexible SWCNT transistors have never been realized on paper substrates, which are widely used, inexpensive, and recyclable. In this study, we fabricated SWCNT thin-film transistors on photo paper substrates. The devices exhibited a high on/off current ratio of more than 10{sup 6} and a field-effect mobility of approximately 3 cm{sup 2}/V·s. The proof-of-concept demonstration indicates that SWCNT transistors on flexible paper substrates could be applied as low-cost and recyclable flexible electronics.
  • A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage tomore » plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.« less
  • A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage tomore » plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.« less
  • A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer ofmore » silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.« less