EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches
Abstract
To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.
- Authors:
-
- ORNL
- Publication Date:
- Research Org.:
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
- Sponsoring Org.:
- USDOE Office of Science (SC)
- OSTI Identifier:
- 1159425
- DOE Contract Number:
- DE-AC05-00OR22725
- Resource Type:
- Conference
- Resource Relation:
- Conference: 2nd USENIX Workshop on Interactions of NVM/Flash with Operating Systems and Workloads (INFLOW), Broomsfield, CO, USA, 20141005, 20141005
- Country of Publication:
- United States
- Language:
- English
- Subject:
- Non-volatile memory; ReRAM; wear-leveling; intra-set write variation; cache lifetime; write endurance
Citation Formats
Mittal, Sparsh, and Vetter, Jeffrey S. EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches. United States: N. p., 2014.
Web.
Mittal, Sparsh, & Vetter, Jeffrey S. EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches. United States.
Mittal, Sparsh, and Vetter, Jeffrey S. 2014.
"EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches". United States. https://www.osti.gov/servlets/purl/1159425.
@article{osti_1159425,
title = {EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches},
author = {Mittal, Sparsh and Vetter, Jeffrey S},
abstractNote = {To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.},
doi = {},
url = {https://www.osti.gov/biblio/1159425},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Wed Jan 01 00:00:00 EST 2014},
month = {Wed Jan 01 00:00:00 EST 2014}
}