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Title: TUNE: Compiler-Directed Automatic Performance Tuning

Abstract

This project has developed compiler-directed performance tuning technology targeting the Cray XT4 Jaguar system at Oak Ridge, which has multi-core Opteron nodes with SSE-3 SIMD extensions, and the Cray XE6 Hopper system at NERSC. To achieve this goal, we combined compiler technology for model-guided empirical optimization for memory hierarchies with SIMD code generation, which have been developed by the PIs over the past several years. We examined DOE Office of Science applications to identify performance bottlenecks and apply our system to computational kernels that operate on dense arrays. Our goal for this performance-tuning technology has been to yield hand-tuned levels of performance on DOE Office of Science computational kernels, while allowing application programmers to specify their computations at a high level without requiring manual optimization. Overall, we aim to make our technology for SIMD code generation and memory hierarchy optimization a crucial component of high-productivity Petaflops computing through a close collaboration with the scientists in national laboratories.

Authors:
 [1]
  1. University of Utah
Publication Date:
Research Org.:
University of Utah
Sponsoring Org.:
USDOE
Contributing Org.:
Argonne National Laboratory, USC/ISI
OSTI Identifier:
1156961
Report Number(s):
DOE-UTAH-03777
DOE Contract Number:  
SC0003777
Resource Type:
Technical Report
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING; autotuning, compiler, SIMD

Citation Formats

Hall, Mary. TUNE: Compiler-Directed Automatic Performance Tuning. United States: N. p., 2014. Web. doi:10.2172/1156961.
Hall, Mary. TUNE: Compiler-Directed Automatic Performance Tuning. United States. doi:10.2172/1156961.
Hall, Mary. Thu . "TUNE: Compiler-Directed Automatic Performance Tuning". United States. doi:10.2172/1156961. https://www.osti.gov/servlets/purl/1156961.
@article{osti_1156961,
title = {TUNE: Compiler-Directed Automatic Performance Tuning},
author = {Hall, Mary},
abstractNote = {This project has developed compiler-directed performance tuning technology targeting the Cray XT4 Jaguar system at Oak Ridge, which has multi-core Opteron nodes with SSE-3 SIMD extensions, and the Cray XE6 Hopper system at NERSC. To achieve this goal, we combined compiler technology for model-guided empirical optimization for memory hierarchies with SIMD code generation, which have been developed by the PIs over the past several years. We examined DOE Office of Science applications to identify performance bottlenecks and apply our system to computational kernels that operate on dense arrays. Our goal for this performance-tuning technology has been to yield hand-tuned levels of performance on DOE Office of Science computational kernels, while allowing application programmers to specify their computations at a high level without requiring manual optimization. Overall, we aim to make our technology for SIMD code generation and memory hierarchy optimization a crucial component of high-productivity Petaflops computing through a close collaboration with the scientists in national laboratories.},
doi = {10.2172/1156961},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {9}
}