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Title: Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses

Abstract

In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.

Inventors:
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1156947
Patent Number(s):
8,832,403
Application Number:
12/796,411
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses. United States: N. p., 2014. Web.
Ohmacht, Martin. Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses. United States.
Ohmacht, Martin. Tue . "Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses". United States. doi:. https://www.osti.gov/servlets/purl/1156947.
@article{osti_1156947,
title = {Generation-based memory synchronization in a multiprocessor system with weakly consistent memory accesses},
author = {Ohmacht, Martin},
abstractNote = {In a multiprocessor system, a central memory synchronization module coordinates memory synchronization requests responsive to memory access requests in flight, a generation counter, and a reclaim pointer. The central module communicates via point-to-point communication. The module includes a global OR reduce tree for each memory access requesting device, for detecting memory access requests in flight. An interface unit is implemented associated with each processor requesting synchronization. The interface unit includes multiple generation completion detectors. The generation count and reclaim pointer do not pass one another.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Sep 09 00:00:00 EDT 2014},
month = {Tue Sep 09 00:00:00 EDT 2014}
}

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Works referenced in this record:

Synchronisation
patent-application, January 2009


Translation-lookaside buffer consistency
journal, June 1990


A Burst Scheduling Access Reordering Mechanism
conference, February 2007