SEGR in SiO$${}_2$$ –Si$$_3$$ N$$_4$$ Stacks
Abstract
This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO2–Si3N4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.
- Authors:
-
- Univ. of Jyvaskyla (Finland). Dept. of Phys.
- European Space Agency (ESTEC), Noordwijk (Netherlands)
- STMicroelectronics Srl, Catania (Italy)
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Publication Date:
- Research Org.:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Org.:
- USDOE National Nuclear Security Administration (NNSA)
- OSTI Identifier:
- 1143834
- Report Number(s):
- SAND2013-8530J
Journal ID: ISSN 0018-9499; 476604
- Grant/Contract Number:
- AC04-94AL85000
- Resource Type:
- Journal Article: Accepted Manuscript
- Journal Name:
- IEEE Transactions on Nuclear Science
- Additional Journal Information:
- Journal Volume: 61; Journal Issue: 4; Journal ID: ISSN 0018-9499
- Publisher:
- Institute of Electrical and Electronics Engineers (IEEE)
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; semi-empirical; Single Event Gate Rupture (SEGR); Modeling; MOS; hboxSiO₂
Citation Formats
Javanainen, Arto, Ferlet-Cavrois, Veronique, Bosser, Alexandre, Jaatinen, Jukka, Kettunen, Heikki, Muschitiello, Michele, Pintacuda, Francesco, Rossi, Mikko, Schwank, James R., Shaneyfelt, Marty R., and Virtanen, Ari. SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks. United States: N. p., 2014.
Web. doi:10.1109/TNS.2014.2303493.
Javanainen, Arto, Ferlet-Cavrois, Veronique, Bosser, Alexandre, Jaatinen, Jukka, Kettunen, Heikki, Muschitiello, Michele, Pintacuda, Francesco, Rossi, Mikko, Schwank, James R., Shaneyfelt, Marty R., & Virtanen, Ari. SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks. United States. https://doi.org/10.1109/TNS.2014.2303493
Javanainen, Arto, Ferlet-Cavrois, Veronique, Bosser, Alexandre, Jaatinen, Jukka, Kettunen, Heikki, Muschitiello, Michele, Pintacuda, Francesco, Rossi, Mikko, Schwank, James R., Shaneyfelt, Marty R., and Virtanen, Ari. 2014.
"SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks". United States. https://doi.org/10.1109/TNS.2014.2303493. https://www.osti.gov/servlets/purl/1143834.
@article{osti_1143834,
title = {SEGR in SiO${}_2$ –Si$_3$ N$_4$ Stacks},
author = {Javanainen, Arto and Ferlet-Cavrois, Veronique and Bosser, Alexandre and Jaatinen, Jukka and Kettunen, Heikki and Muschitiello, Michele and Pintacuda, Francesco and Rossi, Mikko and Schwank, James R. and Shaneyfelt, Marty R. and Virtanen, Ari},
abstractNote = {This work presents experimental SEGR data for MOS-devices, where the gate dielectrics are are made of stacked SiO2–Si3N4 structures. Also a semi-empirical model for predicting the critical gate voltage in these structures under heavy-ion exposure is proposed. Then statistical interrelationship between SEGR cross-section data and simulated energy deposition probabilities in thin dielectric layers is discussed.},
doi = {10.1109/TNS.2014.2303493},
url = {https://www.osti.gov/biblio/1143834},
journal = {IEEE Transactions on Nuclear Science},
issn = {0018-9499},
number = 4,
volume = 61,
place = {United States},
year = {Thu Apr 17 00:00:00 EDT 2014},
month = {Thu Apr 17 00:00:00 EDT 2014}
}
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Cited by: 5 works
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