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Title: Thermal Stressing of InGaP/GaAs HBTs.

Abstract

Abstract not provided.

Authors:
; ; ; ; ; ; ;
Publication Date:
Research Org.:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Org.:
USDOE National Nuclear Security Administration (NNSA)
OSTI Identifier:
1141104
Report Number(s):
SAND2011-2673C
506059
DOE Contract Number:
AC04-94AL85000
Resource Type:
Conference
Resource Relation:
Conference: Proposed for presentation at the 2011 ROCS Workshop held May 16-19, 2011 in Palm Springs, CA.
Country of Publication:
United States
Language:
English

Citation Formats

Baca, Albert G., Fortune, Torben Ray, Gorenz, Alan, Clevenger, Jascinda, Briggs, Ronald D., Patrizi, Gary A., Klem, John Frederick, and Sullivan, Charles T. Thermal Stressing of InGaP/GaAs HBTs.. United States: N. p., 2011. Web.
Baca, Albert G., Fortune, Torben Ray, Gorenz, Alan, Clevenger, Jascinda, Briggs, Ronald D., Patrizi, Gary A., Klem, John Frederick, & Sullivan, Charles T. Thermal Stressing of InGaP/GaAs HBTs.. United States.
Baca, Albert G., Fortune, Torben Ray, Gorenz, Alan, Clevenger, Jascinda, Briggs, Ronald D., Patrizi, Gary A., Klem, John Frederick, and Sullivan, Charles T. Fri . "Thermal Stressing of InGaP/GaAs HBTs.". United States. doi:. https://www.osti.gov/servlets/purl/1141104.
@article{osti_1141104,
title = {Thermal Stressing of InGaP/GaAs HBTs.},
author = {Baca, Albert G. and Fortune, Torben Ray and Gorenz, Alan and Clevenger, Jascinda and Briggs, Ronald D. and Patrizi, Gary A. and Klem, John Frederick and Sullivan, Charles T.},
abstractNote = {Abstract not provided.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Fri Apr 01 00:00:00 EDT 2011},
month = {Fri Apr 01 00:00:00 EDT 2011}
}

Conference:
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  • Abstract not provided.
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  • Flip-chip heterogeneously integrated n-p-n InGaP/GaAs heterojunction bipolar transistors (HBTs) with integrated thermal management on wide-bandgap AlN substrates followed by GaAs substrate removal are demonstrated. Without thermal management, substrate removal after integration significantly aggravates self-heating effects, causing poor I–V characteristics due to excessive device self-heating. An electrothermal codesign scheme is demonstrated that involves simulation (design), thermal characterization, fabrication, and evaluation. Thermoreflectance thermal imaging, electrical-temperature sensitive parameter-based thermometry, and infrared thermography were utilized to assess the junction temperature rise in HBTs under diverse configurations. In order to reduce the thermal resistance of integrated devices, passive cooling schemes assisted by structural modification, i.e.,more » positioning indium bump heat sinks between the devices and the carrier, were employed. By implementing thermal heat sinks in close proximity to the active region of flip-chip integrated HBTs, the junction-to-baseplate thermal resistance was reduced over a factor of two, as revealed by junction temperature measurements and improvement of electrical performance. In conclusion, the suggested heterogeneous integration method accounts for not only electrical but also thermal requirements providing insight into realization of advanced and robust III–V/Si heterogeneously integrated electronics.« less