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Title: Efficient Sorting on the Tilera Manycore Architecture

Abstract

e present an efficient implementation of the radix sort algo- rithm for the Tilera TILEPro64 processor. The TILEPro64 is one of the first successful commercial manycore processors. It is com- posed of 64 tiles interconnected through multiple fast Networks- on-chip and features a fully coherent, shared distributed cache. The architecture has a large degree of flexibility, and allows various optimization strategies. We describe how we mapped the algorithm to this architecture. We present an in-depth analysis of the optimizations for each phase of the algorithm with respect to the processor’s sustained performance. We discuss the overall throughput reached by our radix sort implementation (up to 132 MK/s) and show that it provides comparable or better performance-per-watt with respect to state-of-the art implemen- tations on x86 processors and graphic processing units.

Authors:
; ; ; ;
Publication Date:
Research Org.:
Pacific Northwest National Lab. (PNNL), Richland, WA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1126377
Report Number(s):
PNNL-SA-90686
400470000
DOE Contract Number:  
AC05-76RL01830
Resource Type:
Conference
Resource Relation:
Conference: IEEE 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2012), October 24-26, 2012, New York, 171-178
Country of Publication:
United States
Language:
English
Subject:
Tilera; Radix sort; manycore

Citation Formats

Morari, Alessandro, Tumeo, Antonino, Villa, Oreste, Secchi, Simone, and Valero, Mateo. Efficient Sorting on the Tilera Manycore Architecture. United States: N. p., 2012. Web. doi:10.1109/SBAC-PAD.2012.41.
Morari, Alessandro, Tumeo, Antonino, Villa, Oreste, Secchi, Simone, & Valero, Mateo. Efficient Sorting on the Tilera Manycore Architecture. United States. doi:10.1109/SBAC-PAD.2012.41.
Morari, Alessandro, Tumeo, Antonino, Villa, Oreste, Secchi, Simone, and Valero, Mateo. Wed . "Efficient Sorting on the Tilera Manycore Architecture". United States. doi:10.1109/SBAC-PAD.2012.41.
@article{osti_1126377,
title = {Efficient Sorting on the Tilera Manycore Architecture},
author = {Morari, Alessandro and Tumeo, Antonino and Villa, Oreste and Secchi, Simone and Valero, Mateo},
abstractNote = {e present an efficient implementation of the radix sort algo- rithm for the Tilera TILEPro64 processor. The TILEPro64 is one of the first successful commercial manycore processors. It is com- posed of 64 tiles interconnected through multiple fast Networks- on-chip and features a fully coherent, shared distributed cache. The architecture has a large degree of flexibility, and allows various optimization strategies. We describe how we mapped the algorithm to this architecture. We present an in-depth analysis of the optimizations for each phase of the algorithm with respect to the processor’s sustained performance. We discuss the overall throughput reached by our radix sort implementation (up to 132 MK/s) and show that it provides comparable or better performance-per-watt with respect to state-of-the art implemen- tations on x86 processors and graphic processing units.},
doi = {10.1109/SBAC-PAD.2012.41},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2012},
month = {10}
}

Conference:
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