FleX-3D Wafer Processing for Chip Stacking and Interconnect

Title: FleX-3D Wafer Processing for Chip Stacking and Interconnect

Technical Report · Thu Mar 20 00:00:00 EDT 2014

OSTI ID:1123902

Wilson, Dale G. ^[1]

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Research Organization:: American Semiconductor, Inc., Boise, ID (United States)

Sponsoring Organization:: USDOE Office of Energy Efficiency and Renewable Energy (EERE), Weatherization and Intergovernmental Program (EE-2K); USDOE Office of Science (SC), High Energy Physics (HEP); USDOE Office of Science (SC), Nuclear Physics (NP)

Three wafer stacking for 3D integration.

Technical Report · Tue Nov 01 00:00:00 EDT 2011 · OSTI ID:1123902

Greth, K Douglas; Ford, Christine L; Lantz, Jeffrey W; +5 more

Process for 3D chip stacking

Patent · Thu Jan 01 00:00:00 EST 1998 · OSTI ID:1123902

Malba, Vincent

Process for 3D chip stacking

Patent · Tue Nov 10 00:00:00 EST 1998 · OSTI ID:1123902

Malba, V

42 ENGINEERING
3D integrated circuits
chip stacking
through-silicon vias
silicon pixel detectors
ultra thin CMOS
vertical integration