A Survey of Architectural Techniques For Improving Cache Power Efficiency
- ORNL
Modern processors are using increasingly larger sized on-chip caches. Also, with each CMOS technology generation, there has been a significant increase in their leakage energy consumption. For this reason, cache power management has become a crucial research issue in modern processor design. To address this challenge and also meet the goals of sustainable computing, researchers have proposed several techniques for improving energy efficiency of cache architectures. This paper surveys recent architectural techniques for improving cache power efficiency and also presents a classification of these techniques based on their characteristics. For providing an application perspective, this paper also reviews several real-world processor chips that employ cache energy saving techniques. The aim of this survey is to enable engineers and researchers to get insights into the techniques for improving cache power efficiency and motivate them to invent novel solutions for enabling low-power operation of caches.
- Research Organization:
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
- Sponsoring Organization:
- USDOE Office of Science (SC)
- DOE Contract Number:
- DE-AC05-00OR22725
- OSTI ID:
- 1110983
- Journal Information:
- Sustainable Computing: Informatics and Systems, Journal Name: Sustainable Computing: Informatics and Systems
- Country of Publication:
- United States
- Language:
- English
Similar Records
A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches
Architectural Techniques For Managing Non-volatile Caches