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Title: Distributed performance counters

Abstract

A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.

Inventors:
; ; ;
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY, USA
Sponsoring Org.:
USDOE
OSTI Identifier:
1108972
Patent Number(s):
8,595,389
Application Number:
12/684,738
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:  
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Davis, Kristan D, Evans, Kahn C, Gara, Alan, and Satterfield, David L. Distributed performance counters. United States: N. p., 2013. Web.
Davis, Kristan D, Evans, Kahn C, Gara, Alan, & Satterfield, David L. Distributed performance counters. United States.
Davis, Kristan D, Evans, Kahn C, Gara, Alan, and Satterfield, David L. Tue . "Distributed performance counters". United States. doi:. https://www.osti.gov/servlets/purl/1108972.
@article{osti_1108972,
title = {Distributed performance counters},
author = {Davis, Kristan D and Evans, Kahn C and Gara, Alan and Satterfield, David L},
abstractNote = {A plurality of first performance counter modules is coupled to a plurality of processing cores. The plurality of first performance counter modules is operable to collect performance data associated with the plurality of processing cores respectively. A plurality of second performance counter modules are coupled to a plurality of L2 cache units, and the plurality of second performance counter modules are operable to collect performance data associated with the plurality of L2 cache units respectively. A central performance counter module may be operable to coordinate counter data from the plurality of first performance counter modules and the plurality of second performance modules, the a central performance counter module, the plurality of first performance counter modules, and the plurality of second performance counter modules connected by a daisy chain connection.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Nov 26 00:00:00 EST 2013},
month = {Tue Nov 26 00:00:00 EST 2013}
}

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