Hardware packet pacing using a DMA in a parallel computer

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

Hardware packet pacing using a DMA in a parallel computer

Patent · 13 August 2013

OSTI ID:1092967

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

Research Organization:: International Business Machines Corporation (Armonk, NY)

Sponsoring Organization:: USDOE

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 8,509,255

Application Number:: 11/768,682

OSTI ID:: 1092967

Country of Publication:: United States

Language:: English

References (8)

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Synchronization, coherence, and event ordering in multiprocessors Dubois, M.; Scheurich, C.; Briggs, F. A. Computer, Vol. 21, Issue 2 https://doi.org/10.1109/2.15	journal	February 1988
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Optimization of MPI collective communication on BlueGene/L systems Almási, George; Heidelberger, Philip; Archer, Charles J. Proceedings of the 19th annual international conference on Supercomputing - ICS '05 https://doi.org/10.1145/1088149.1088183	conference	January 2005
Intel 870: a building block for cost-effective, scalable servers Briggs, F.; Cekleov, M.; Creta, K. IEEE Micro, Vol. 22, Issue 2 https://doi.org/10.1109/MM.2002.997878	journal	March 2002
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