Combined group ECC protection and subgroup parity protection
A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.
- Research Organization:
- International Business Machines Corporation (Armonk, NY)
- Sponsoring Organization:
- USDOE
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,468,416
- Application Number:
- 11/768,527
- OSTI ID:
- 1084071
- Country of Publication:
- United States
- Language:
- English
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