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Title: Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management

Abstract

Local thermal hot-spots in microprocessors lead to worst case provisioning of global cooling resources, especially in large-scale systems. However, efficiency of cooling solutions degrade non-linearly with supply temperature, resulting in high power consumption and cost in cooling - 50 {approx} 100% of IT power. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots, where applying current to a superlattice film deposited between silicon and the heat spreader results in a Peltier effect that spreads the heat and lowers the temperature of the hot-spot significantly to improve chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sources, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multiscale analysis shows that, for a typical data center, TECs allow global coolers to operatemore » at higher temperatures without degrading chip lifetime, and thus save {approx}27% cooling power on average while providing the same processor reliability as a data center running at 288K.« less

Authors:
; ; ; ;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1018774
Report Number(s):
LLNL-CONF-474345
TRN: US201114%%322
DOE Contract Number:  
W-7405-ENG-48
Resource Type:
Conference
Resource Relation:
Conference: Presented at: International Symposium on Computer Architecture, San Jose, CA, United States, Jun 04 - Jun 08, 2011
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; AVAILABILITY; COMPUTER ARCHITECTURE; DIFFUSION; EFFICIENCY; HEAT EXCHANGERS; HOT SPOTS; LIFETIME; MANAGEMENT; MICROPROCESSORS; MITIGATION; RELIABILITY; SILICON; SIMULATION; SUPERLATTICES; THERMOELECTRIC COOLERS

Citation Formats

Biswas, S, Tiwari, M, Theogarajan, L, Sherwood, T P, and Chong, F T. Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management. United States: N. p., 2010. Web.
Biswas, S, Tiwari, M, Theogarajan, L, Sherwood, T P, & Chong, F T. Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management. United States.
Biswas, S, Tiwari, M, Theogarajan, L, Sherwood, T P, and Chong, F T. Thu . "Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management". United States. https://www.osti.gov/servlets/purl/1018774.
@article{osti_1018774,
title = {Fighting Fire with Fire: Modeling the Datacenter-Scale Effects of Targeted Superlattice Thermal Management},
author = {Biswas, S and Tiwari, M and Theogarajan, L and Sherwood, T P and Chong, F T},
abstractNote = {Local thermal hot-spots in microprocessors lead to worst case provisioning of global cooling resources, especially in large-scale systems. However, efficiency of cooling solutions degrade non-linearly with supply temperature, resulting in high power consumption and cost in cooling - 50 {approx} 100% of IT power. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots, where applying current to a superlattice film deposited between silicon and the heat spreader results in a Peltier effect that spreads the heat and lowers the temperature of the hot-spot significantly to improve chip reliability. In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sources, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multiscale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save {approx}27% cooling power on average while providing the same processor reliability as a data center running at 288K.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2010},
month = {11}
}

Conference:
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