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Title: An analog memory integrated circuit for waveform acquisition up to 900 MHz

Abstract

The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-{mu}m complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The measured rms cel pedestal variation in a channel after baseline subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.

Authors:
 [1];  [2]
  1. Stanford Linear Accelerator Center, Menlo Park, CA (United States)
  2. Stanford Univ., CA (United States). Center for Integrated Systems
Publication Date:
Research Org.:
Stanford Linear Accelerator Center, Menlo Park, CA (United States)
Sponsoring Org.:
USDOE, Washington, DC (United States)
OSTI Identifier:
10136576
Report Number(s):
SLAC-PUB-6402; CONF-931107-36
ON: DE94009020; TRN: 94:007466
DOE Contract Number:  
AC03-76SF00515
Resource Type:
Conference
Resource Relation:
Conference: 1993 IEEE nuclear science symposium and medical imaging conference,San Francisco, CA (United States),2-5 Nov 1993; Other Information: PBD: Dec 1993
Country of Publication:
United States
Language:
English
Subject:
43 PARTICLE ACCELERATORS; 42 ENGINEERING; 99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; WAVE FORMS; DATA ACQUISITION SYSTEMS; MEMORY DEVICES; INTEGRATED CIRCUITS; MOS TRANSISTORS; 430303; 426000; 990200; EXPERIMENTAL FACILITIES AND EQUIPMENT; COMPONENTS, ELECTRON DEVICES AND CIRCUITS; MATHEMATICS AND COMPUTERS

Citation Formats

Haller, G M, and Wooley, B A. An analog memory integrated circuit for waveform acquisition up to 900 MHz. United States: N. p., 1993. Web.
Haller, G M, & Wooley, B A. An analog memory integrated circuit for waveform acquisition up to 900 MHz. United States.
Haller, G M, and Wooley, B A. Wed . "An analog memory integrated circuit for waveform acquisition up to 900 MHz". United States. https://www.osti.gov/servlets/purl/10136576.
@article{osti_10136576,
title = {An analog memory integrated circuit for waveform acquisition up to 900 MHz},
author = {Haller, G M and Wooley, B A},
abstractNote = {The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-{mu}m complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The measured rms cel pedestal variation in a channel after baseline subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1993},
month = {12}
}

Conference:
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