Low latency counter event indication

Patent · Tue Aug 24 00:00:00 EDT 2010

OSTI ID:1013615

Gara, Alan G ^[1]; Salapura, Valentina ^[2]

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1. Mount Kisco, NY
2. Chappaqua, NY

A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding "interrupt arm" bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

• Research Organization: International Business Machines Corp., Armonk, NY (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: B542702
• Assignee: International Business Machines Corporation (Armonk, NY)
• Patent Number(s): 7,782,995
• Application Number: 12/130,724
• OSTI ID: 1013615
• Country of Publication: United States
• Language: English