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Programmable partitioning for high-performance coherence domains in a multiprocessor system

Patent ·
OSTI ID:1012661
 [1];  [2]
  1. Ridgefield, CT
  2. Chappaqua, NY
+ Show Author Affiliations
A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache, and the snoop units are provided for supporting cache coherency in the multiprocessor system. Each of the snoop units is connected to a respective one of the processing units and to all of the other snoop units. The multiprocessor computing system further includes a partitioning system for using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size processing groups. Preferably, when the processor units are partitioned into these processing groups, the partitioning system also configures the snoop units to maintain cache coherency within each of said groups.
Research Organization:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
7,877,551
Application Number:
11/768,532
OSTI ID:
1012661
Country of Publication:
United States
Language:
English

References (8)

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Performance evaluation of adaptive MPI
  • Huang, Chao; Zheng, Gengbin; Kalé, Laxmikant
  • Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming - PPoPP '06 https://doi.org/10.1145/1122971.1122976
conference January 2006
Synchronization, coherence, and event ordering in multiprocessors journal February 1988
Blue Gene/L advanced diagnostics environment journal March 2005
Optimization of MPI collective communication on BlueGene/L systems conference January 2005
Intel 870: a building block for cost-effective, scalable servers journal March 2002
Directory-based cache coherence in large-scale multiprocessors journal June 1990
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures journal August 2005

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Related Subjects

97 MATHEMATICS AND COMPUTING