Software Barrier Performance on Dual Quad-Core Opterons

Conference · Tue Jul 01 00:00:00 EDT 2008

DOI:https://doi.org/10.1109/NAS.2008.27· OSTI ID:1008861

Jie Chen, William Watson

Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs through on-chip multi-threading. However, a relative slow software barrier can hinder the performance of a data-parallel scientific application on a multi-core system. In this paper we study the performance of different software barrier algorithms on a server based on newly introduced AMD quad-core Opteron processors. We study how the memory architecture and the cache coherence protocol of the system influence the performance of barrier algorithms. We present an optimized barrier algorithm derived from the queue-based barrier algorithm. We find that the optimized barrier algorithm achieves speedup of 1.77 over the original queue-based algorithm. In addition, it has speedup of 2.39 over the software barrier generated by the Intel OpenMP compiler.

• Research Organization: Thomas Jefferson National Accelerator Facility (TJNAF), Newport News, VA (United States)
• Sponsoring Organization: USDOE Office of Science (SC)
• DOE Contract Number: AC05-06OR23177
• OSTI ID: 1008861
• Report Number(s): JLAB-IT-08-04; DOE/OR/23177-1502; TRN: US201108%%196
• Resource Relation: Conference: 2008 International Conference on Networking, Architecture, and Storage. NAS '08, 12-14 June 2008, Chongqing, China
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ALGORITHMS
COMPUTER ARCHITECTURE
PERFORMANCE
STORAGE
COMPUTER NETWORKS
Linux
memory architecture
multi-threading
program compilers
Intel OpenMP compiler
Linux clusters
cache coherence protocol
data-parallel scientific application
dual quad-core Opterons
memory architecture
multicore processors
multithreaded programs
onchip multithreading
queue-based barrier algorithm
software barrier performance
Centralized Barrier
OpenMP
Opteron
Queue-based Barrier
Software Barrier