Radiation Hardening of CMOS Microelectronics
A unique methodology, silicon transfer to arbitrary substrates, has been developed under this program and is being investigated as a technique for significantly increasing the radiation insensitivity of limited quantities of conventional silicon microelectronic circuits. In this approach, removal of the that part of the silicon substrate not required for circuit operation is carried out, following completion of the circuit fabrication process. This post-processing technique is therefore applicable to state-of-the-art ICs, effectively bypassing the 3-generation technology/performance gap presently separating today's electronics from available radiation-hard electronics. Also, of prime concern are the cost savings that result by eliminating the requirement for costly redesign of commercial circuits for Rad-hard applications. Successful deployment of this technology will result in a major impact on the radiation hard electronics community in circuit functionality, design and software availability and fabrication costs.
- Research Organization:
- Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE Office of Defense Programs (DP) (US)
- DOE Contract Number:
- W-7405-Eng-48
- OSTI ID:
- 792429
- Report Number(s):
- UCRL-ID-137665; TRN: US0300428
- Resource Relation:
- Other Information: PBD: 20 Feb 2000
- Country of Publication:
- United States
- Language:
- English
Similar Records
Use of COTS microelectronics in radiation environments
Center for Energy Efficient Materials (CEEM) (Final Technical Report)