Reliability concerns with logical constants in Xilinx FPGA designs
- Los Alamos National Laboratory
- JPL
- XILINX
In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.
- Research Organization:
- Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-06NA25396
- OSTI ID:
- 990795
- Report Number(s):
- LA-UR-09-04566; LA-UR-09-4566; TRN: US201020%%606
- Resource Relation:
- Conference: IEEE NSREC 2009 ; July 19, 2009 ; Quebec City, Quebec, Canada
- Country of Publication:
- United States
- Language:
- English
Similar Records
Test results of an ITER relevant FPGA when irradiated with neutrons
SEU mitigation for half-latches in xilinx virtex FPGAs.