Single-poly EEPROM cell with lightly doped MOS capacitors
Abstract
An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.
- Inventors:
-
- New Hope, MN
- Maple Grove, MN
- Mound, MN
- Golden Valley, MN
- Publication Date:
- Research Org.:
- National Energy Technology Laboratory (NETL), Pittsburgh, PA, Morgantown, WV (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 981823
- Patent Number(s):
- 7,378,705
- Application Number:
- 11/217,829
- Assignee:
- Honeywell International, Inc. (Morristown, NJ)
- DOE Contract Number:
- FC26-03NT41834
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, and Gardner, Gary R. Single-poly EEPROM cell with lightly doped MOS capacitors. United States: N. p., 2008.
Web.
Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, & Gardner, Gary R. Single-poly EEPROM cell with lightly doped MOS capacitors. United States.
Riekels, James E, Lucking, Thomas B, Larsen, Bradley J, and Gardner, Gary R. 2008.
"Single-poly EEPROM cell with lightly doped MOS capacitors". United States. https://www.osti.gov/servlets/purl/981823.
@article{osti_981823,
title = {Single-poly EEPROM cell with lightly doped MOS capacitors},
author = {Riekels, James E and Lucking, Thomas B and Larsen, Bradley J and Gardner, Gary R},
abstractNote = {An Electrically Erasable Programmable Read Only Memory (EEPROM) memory cell and a method of operation are disclosed for creating an EEPROM memory cell in a standard CMOS process. A single polysilicon layer is used in combination with lightly doped MOS capacitors. The lightly doped capacitors employed in the EEPROM memory cell can be asymmetrical in design. Asymmetrical capacitors reduce area. Further capacitance variation caused by inversion can also be reduced by using multiple control capacitors. In addition, the use of multiple tunneling capacitors provides the benefit of customized tunneling paths.},
doi = {},
url = {https://www.osti.gov/biblio/981823},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue May 27 00:00:00 EDT 2008},
month = {Tue May 27 00:00:00 EDT 2008}
}
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