KPiX, An Array of Self Triggered Charge Sensitive Cells Generating Digital Time and Amplitude Information
The Silicon Detector proposed for the International Linear Collider (ILC) requires electronic read-out that can be tightly coupled to the silicon detectors envisioned for the tracker and the electromagnetic calorimeter. The KPiX is a 1024-channel read-out chip that bump-bonds to the detector and communicates through a few digital signals, power, and detector bias. The KPiX front-end is a low-noise dual-range charge-amplifier with a dynamic range of 17 bit, achieved by autonomous switching of the feedback capacitor. The device takes advantage of the ILC duty cycle of 1 ms trains at 5 Hz rate by lowering the supply current after the data acquisition cycle for an average power consumption of <20 {micro}W/channel. During the 1 ms train, up to four events exceeding a programmable threshold can be stored, the amplitude as a voltage on a capacitor for subsequent digitization, the event time in digital format. The chip can be configured for other than ILC applications.
- Research Organization:
- SLAC National Accelerator Lab., Menlo Park, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC02-76SF00515
- OSTI ID:
- 944071
- Report Number(s):
- SLAC-PUB-13462; TRN: US0900509
- Resource Relation:
- Conference: Presented at 2008 IEEE Nuclear Science Symposium (NSS) and Medical Imaging Conference (MIC) and 16th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors (RTSD), Dresden, Germany, 18-25 Oct 2008
- Country of Publication:
- United States
- Language:
- English
Similar Records
First results of the silicon telescope using an 'artificial retina' for fast track finding
Performance of the CAMEX64 silicon strip readout chip