3-D readout-electronics packaging for high-bandwidth massively paralleled imager
Abstract
Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.
- Inventors:
-
- Los Alamos, NM
- Albuquerque, NM
- Publication Date:
- Research Org.:
- Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 921054
- Patent Number(s):
- 7,309,878
- Application Number:
- 10/901,309
- Assignee:
- U.S. Department of Energy (Washington, DC)
- DOE Contract Number:
- W-7405-ENG-36
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
Citation Formats
Kwiatkowski, Kris, and Lyke, James. 3-D readout-electronics packaging for high-bandwidth massively paralleled imager. United States: N. p., 2007.
Web.
Kwiatkowski, Kris, & Lyke, James. 3-D readout-electronics packaging for high-bandwidth massively paralleled imager. United States.
Kwiatkowski, Kris, and Lyke, James. 2007.
"3-D readout-electronics packaging for high-bandwidth massively paralleled imager". United States. https://www.osti.gov/servlets/purl/921054.
@article{osti_921054,
title = {3-D readout-electronics packaging for high-bandwidth massively paralleled imager},
author = {Kwiatkowski, Kris and Lyke, James},
abstractNote = {Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.},
doi = {},
url = {https://www.osti.gov/biblio/921054},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Dec 18 00:00:00 EST 2007},
month = {Tue Dec 18 00:00:00 EST 2007}
}