A flexible analog memory address list manager/controller for PHENIX
A programmable analog memory address list manager/controller has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 112 ns. Addresses are handled such that up to 5 Level-1 events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam event data packets. Full usage in all PHENIX analog memory-based detector sub-systems is accomplished by the use of detector-specific programmable parameters -- the number of data samples per Level-1 trigger valid and the swnple spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including design simulations, timing information, and test results from a full implementation using programmable logic devices.
- Research Organization:
- Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC05-84OR21400
- OSTI ID:
- 90090
- Report Number(s):
- CONF-951073-2; ON: DE95012875; TRN: 95:017623
- Resource Relation:
- Conference: IEEE nuclear science symposium and medical imaging conference, San Francisco, CA (United States), 21-28 Oct 1995; Other Information: PBD: [1995]
- Country of Publication:
- United States
- Language:
- English
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