Gated integrator with signal baseline subtraction

Patent · Mon Jan 01 00:00:00 EST 1996

OSTI ID:870742

Wang, Xucheng ^[1]

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1. Lisle, IL

An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

• Research Organization: Argonne National Laboratory (ANL), Argonne, IL (United States)
• DOE Contract Number: W-31109-ENG-38
• Assignee: University of Chicago (Chicago, IL)
• Patent Number(s): US 5585756
• OSTI ID: 870742
• Country of Publication: United States
• Language: English

Related Subjects

gated
integrator
signal
baseline
subtraction
ultrafast
precision
opamp
differential
inputs
integrated
applied
input
network
indicative
dc
offset
component
pair
electronic
switches
networks
define
integrating
period
closed
substantially
symmetrically
constructed
matched
components
error
introduced
appear
circuits
hence
nullified
common
mode
rejection
provided
sample
hold
circuit
actuated
begins
symmetrical
configuration
improves
accuracy
speed
balancing
errors
permitting
switching
elements
opamps
time
constant
eliminates
caused
single
window
common mode
electronic switches
input signal
signal indicative
time constant
hold circuit
substantially eliminates
substantially symmetrical
substantially eliminate
electronic switch
switching elements
error components
differential inputs
input network
integrating circuit
gated integrator
switching element
speed switching
differential input
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