Electrochemical planarization

Patent · Fri Jan 01 00:00:00 EST 1993

OSTI ID:868983

Bernhardt, Anthony F ^[1]; Contolini, Robert J ^[2]

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1. Berkeley, CA
2. Pleasanton, CA

In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• DOE Contract Number: W-7405-ENG-48
• Assignee: United States of America as represented by United States (Washington, DC)
• Patent Number(s): US 5256565
• OSTI ID: 868983
• Country of Publication: United States
• Language: English

Related Subjects

electrochemical
planarization
process
fabricating
planarized
film
metal
interconnects
integrated
circuit
structures
layer
etched
underlying
dielectric
electropolishing
milling
procedure
reduces
processing
time
hours
minutes
allows
batch
multiple
wafers
interconnect
flush
processing time
dielectric layer
metal layer
integrated circuit
multiple wafers
batch processing
batch process
film metal
circuit structure
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