High resolution digital delay timer

Patent · Fri Jan 01 00:00:00 EST 1988

OSTI ID:866473

Martin, Albert D ^[1]

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1. Los Alamos, NM

Method and apparatus are provided for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses. A first lumped constant delay (20) provides a first output signal (24) at predetermined interpolation intervals corresponding to the desired high resolution time interval. Latching circuits (26, 28) latch the high resolution data (24) to form a first synchronizing data set (60). A selected time interval has been preset to internal counters (142, 146, 154) and corrected for circuit propagation delay times having the same order of magnitude as the desired high resolution. Internal system clock pulses (32, 34) count down the counters to generate an internal pulse delayed by an interval which is functionally related to the preset time interval. A second LCD (184) corrects the internal signal with the high resolution time delay. A second internal pulse is then applied to a third LCD (74) to generate a second set of synchronizing data (76) which is complementary with the first set of synchronizing data (60) for presentation to logic circuits (64). The logic circuits (64) further delay the internal output signal (72) to obtain a proper phase relationship of an output signal (80) with the internal pulses (32, 34). The final delayed output signal (80) thereafter enables the output pulse generator (82) to produce the desired output pulse (84) at the preset time delay interval following input of the trigger pulse (10, 12).

• Research Organization: Los Alamos National Laboratory (LANL), Los Alamos, NM (United States)
• DOE Contract Number: W-7405-ENG-36
• Assignee: United States of America as represented by United States (Washington, DC)
• Patent Number(s): US 4719375
• OSTI ID: 866473
• Country of Publication: United States
• Language: English

Related Subjects

resolution
digital
delay
timer
method
apparatus
provided
generating
output
pulse
following
trigger
time
interval
preset
relative
available
supplied
clock
pulses
lumped
constant
20
provides
signal
24
predetermined
interpolation
intervals
corresponding
desired
latching
circuits
26
28
latch
data
form
synchronizing
set
60
selected
internal
counters
142
146
154
corrected
circuit
propagation
times
magnitude
32
34
count
generate
delayed
functionally
related
lcd
184
corrects
applied
third
74
76
complementary
presentation
logic
64
72
obtain
proper
phase
relationship
80
final
thereafter
enables
generator
82
produce
84
input
10
12
trigger pulse
clock pulse
selected time
logic circuits
propagation delay
functionally related
time delay
pulse generator
output pulse
output signal
data set
time interval
clock pulses
delay time
desired output
logic circuit
resolution time
phase relationship
delay times
resolution available
resolution digital
resolution data
lumped constant
digital delay
/327/377/