Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays
At Jefferson Lab, we have been evaluating soft core processors running an EPICS IOC over {mu}Clinux on our custom hardware. A soft core processor is a flexible CPU architecture that is configured in the FPGA as opposed to a hard core processor which is fixed in silicon. Combined with an on-board Ethernet port, the technology incorporates the IOC and digital control hardware within a single FPGA. By eliminating the general purpose computer IOC, the designer is no longer tied to a specific platform, e.g. PC, VME, or VXI, to serve as the intermediary between the high level controls and the field hardware. This paper will discuss the design and development process as well as specific applications for JLab's next generation low-level RF controls and Machine Protection Systems.
- Research Organization:
- TJNAF (Thomas Jefferson National Accelerator Facility, Newport News, VA)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC05-84ER40150
- OSTI ID:
- 850209
- Report Number(s):
- JLAB-ACO-05-417; DOE/ER/40150-3585; TRN: US0504270
- Resource Relation:
- Conference: ICALEPCS 2005, 10-15 Oct 2005, Geneva, Switzerland
- Country of Publication:
- United States
- Language:
- English
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