Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001
Abstract
The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.
- Authors:
- Publication Date:
- Research Org.:
- NanoSciences Corporation, Oxford, CT (US)
- Sponsoring Org.:
- USDOE Office of Energy Research (ER) (US)
- OSTI Identifier:
- 808738
- Report Number(s):
- DOE/ER/83054-1
TRN: US200311%%59
- DOE Contract Number:
- FG02-00ER83054
- Resource Type:
- Technical Report
- Resource Relation:
- Other Information: PBD: 31 Mar 2001; PBD: 31 Mar 2001
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 42 ENGINEERING; SILICON; THICKNESS; ELECTRONIC CIRCUITS; CONNECTORS; PROGRESS REPORT; ELECTRIC CONTACTS; MINIATURIZATION
Citation Formats
Beetz, C P, Steinbeck, J, and Hsueh, K L. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001. United States: N. p., 2001.
Web. doi:10.2172/808738.
Beetz, C P, Steinbeck, J, & Hsueh, K L. Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001. United States. https://doi.org/10.2172/808738
Beetz, C P, Steinbeck, J, and Hsueh, K L. 2001.
"Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001". United States. https://doi.org/10.2172/808738. https://www.osti.gov/servlets/purl/808738.
@article{osti_808738,
title = {Micromachined VLSI 3D electronics. Final report for period September 1, 2000 - March 31, 2001},
author = {Beetz, C P and Steinbeck, J and Hsueh, K L},
abstractNote = {The phase I program investigated the construction of electronic interconnections through the thickness of a silicon wafer. The novel aspects of the technology are that the length-to-width ratio of the channels is as high as 100:1, so that the minimum amount of real estate is used for contact area. Constructing a large array of these through-wafer interconnections will enable two circuit die to be coupled on opposite sides of a silicon circuit board providing high speed connection between the two.},
doi = {10.2172/808738},
url = {https://www.osti.gov/biblio/808738},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Sat Mar 31 00:00:00 EST 2001},
month = {Sat Mar 31 00:00:00 EST 2001}
}
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