Ion implantation processing for high-speed GaAs JFETs
GaAs Junction Field Effect Transistors (JFETs) offer a higher gate turn-on voltage, resulting in a better noise margin and reduced power dissipation, than the more widely employed GaAs MESFET. The primary reason the JFET has not been more widely used is the speed penalty associated with the gate/channel junction and corresponding gate length broadening. We present the ion implantation processes used for a self-aligned, all ion-implanted, GaAs JFET that minimizes the speed penalty for the JFET while maintaining the advantageous higher gate turn-on voltage. Process characterization of the p{sub +}-gate implant done with either Mg, Zn, or Cd along with the co-implantation of P is presented. In addition, a novel backside channel confinement technology employing ion-implanted carbon is discussed. Complete JFET device results are reported.
- Research Organization:
- Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
- Sponsoring Organization:
- USDOE, Washington, DC (United States)
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 80700
- Report Number(s):
- SAND-95-0084C; CONF-950518-11; ON: DE95013834
- Resource Relation:
- Conference: 187. meeting of the Electrochemical Society, Reno, NV (United States), 21-26 May 1995; Other Information: PBD: [1995]
- Country of Publication:
- United States
- Language:
- English
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