Memory-intensive benchmarks: IRAM vs. cache-based machines
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic structures, and the ratio of computation to memory operation.
- Research Organization:
- Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States)
- Sponsoring Organization:
- USDOE Director, Office of Science (US)
- DOE Contract Number:
- AC03-76SF00098
- OSTI ID:
- 788083
- Report Number(s):
- LBNL-48979; R&D Project: 365958; TRN: AH200135%%149
- Resource Relation:
- Conference: International Parallel and Distributed Processing Symposium, Fort Lauderdale, FL (US), 04/15/2002--04/19/2002; Other Information: PBD: 29 Sep 2001
- Country of Publication:
- United States
- Language:
- English
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