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Title: First level trigger processor for the ZEUS calorimeter

Conference ·
OSTI ID:7247474
; ; ;  [1]; ;  [2]
  1. Argonne National Lab., IL (USA)
  2. Wisconsin Univ., Madison, WI (USA). Dept. of Physics

This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs.

Research Organization:
Argonne National Lab., IL (USA)
Sponsoring Organization:
DOE/ER
DOE Contract Number:
W-31109-ENG-38
OSTI ID:
7247474
Report Number(s):
ANL-HEP-CP-90-2; CONF-900143-29; ON: DE90007793; TRN: 90-008949
Resource Relation:
Conference: Institute for Electronic and Electrical Engineers (IEEE) nuclear science symposium, San Francisco, CA (USA), 15-19 Jan 1990
Country of Publication:
United States
Language:
English

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