The scalable coherent interface, IEEE P1596, status and possible applications to data acquisition and physics

Conference · Mon Jan 01 00:00:00 EST 1990

OSTI ID:7070485

Gustavson, D B

IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics. 7 refs.

• Research Organization: Stanford Linear Accelerator Center, Menlo Park, CA (USA)
• Sponsoring Organization: DOE/ER
• DOE Contract Number: AC03-76SF00515
• OSTI ID: 7070485
• Report Number(s): SLAC-PUB-5119; CONF-900143-26; ON: DE90006454; TRN: 90-007116
• Resource Relation: Conference: Institute for Electronic and Electrical Engineers (IEEE) nuclear science symposium, San Francisco, CA (USA), 22-26 Jan 1990
• Country of Publication: United States
• Language: English

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